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https://codeberg.org/canoeboot/cbmk.git
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a710f63df3
Set the U-Boot revision to the commit hash for v2025.04, and rebase the patches for the default U-Boot tree to accommodate for upstream changes: - The SPL/TPL/VPL phases are being unified under the xPL name, so there's a config rename. - Some test macros were renamed, for the video-related patches. - Add some missing hunks for video damage series. - Upstream Makefile adds another argument to the binman call. - The SWIG related patch is merged upstream, drop it. I'm not sure if src/u-boot/* directories are regenerated on new builds, so it may be necessary to remove them manually after applying this. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
100 lines
4 KiB
Diff
100 lines
4 KiB
Diff
From ee94f55d37fc8c133faa5055184f75f99830cfdc Mon Sep 17 00:00:00 2001
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From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
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Date: Fri, 8 Oct 2021 17:33:22 +0300
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Subject: [PATCH] clk: rockchip: rk3399: Set hardcoded clock rates same as
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devicetree
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Update hardcoded RK3399 clock rate definitions to match those in its
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devicetree (rk3399.dtsi), based on clock-controller assigned-clocks.
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Add and initialize NPLL since it's on that list, though nothing seems to
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use it in the driver so far.
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Also update VOP ACLK to 400MHz as it divides from CPLL (now 800MHz).
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All this stops the displayed vendor bitmap from getting disfigured
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when chainloading U-Boot from coreboot+depthcharge (as RW_LEGACY).
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Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
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Link: https://github.com/alpernebbi/u-boot/commit/7e73b7a7550cfdd22a1413c263026e41e56e7617
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---
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.../include/asm/arch-rockchip/cru_rk3399.h | 19 ++++++++++---------
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drivers/clk/rockchip/clk_rk3399.c | 10 ++++++----
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2 files changed, 16 insertions(+), 13 deletions(-)
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diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
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index d941a129f3e5..54035c0df1f3 100644
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--- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
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+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
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@@ -69,7 +69,8 @@ check_member(rockchip_cru, sdio1_con[1], 0x594);
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#define LPLL_HZ (600*MHz)
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#define BPLL_HZ (600*MHz)
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#define GPLL_HZ (594*MHz)
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-#define CPLL_HZ (384*MHz)
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+#define CPLL_HZ (800*MHz)
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+#define NPLL_HZ (1000*MHz)
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#define PPLL_HZ (676*MHz)
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#define PMU_PCLK_HZ (48*MHz)
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@@ -82,16 +83,16 @@ check_member(rockchip_cru, sdio1_con[1], 0x594);
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#define ATCLK_CORE_B_HZ (300*MHz)
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#define PCLK_DBG_B_HZ (100*MHz)
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-#define PERIHP_ACLK_HZ (148500*KHz)
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-#define PERIHP_HCLK_HZ (148500*KHz)
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-#define PERIHP_PCLK_HZ (37125*KHz)
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+#define PERIHP_ACLK_HZ (150*MHz)
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+#define PERIHP_HCLK_HZ (75*MHz)
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+#define PERIHP_PCLK_HZ (37500*KHz)
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-#define PERILP0_ACLK_HZ (99000*KHz)
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-#define PERILP0_HCLK_HZ (99000*KHz)
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-#define PERILP0_PCLK_HZ (49500*KHz)
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+#define PERILP0_ACLK_HZ (100*MHz)
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+#define PERILP0_HCLK_HZ (100*MHz)
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+#define PERILP0_PCLK_HZ (50*MHz)
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-#define PERILP1_HCLK_HZ (99000*KHz)
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-#define PERILP1_PCLK_HZ (49500*KHz)
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+#define PERILP1_HCLK_HZ (100*MHz)
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+#define PERILP1_PCLK_HZ (50*MHz)
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#define PWM_CLOCK_HZ PMU_PCLK_HZ
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diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
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index 6e87db18be07..1b8ffe9e794e 100644
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--- a/drivers/clk/rockchip/clk_rk3399.c
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+++ b/drivers/clk/rockchip/clk_rk3399.c
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@@ -53,10 +53,11 @@ struct pll_div {
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.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
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.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
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-static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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-static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
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+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
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+static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 3, 1);
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+static const struct pll_div npll_init_cfg = PLL_DIVISORS(NPLL_HZ, 1, 3, 1);
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#if !defined(CONFIG_XPL_BUILD)
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-static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
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+static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 3, 2, 1);
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#endif
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static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
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@@ -681,7 +682,7 @@ static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
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static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
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{
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struct pll_div vpll_config = {0};
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- int aclk_vop = 198 * MHz;
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+ int aclk_vop = 400 * MHz;
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void *aclkreg_addr, *dclkreg_addr;
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u32 div;
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@@ -1394,6 +1395,7 @@ static void rkclk_init(struct rockchip_cru *cru)
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/* configure gpll cpll */
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rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
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rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
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+ rkclk_set_pll(&cru->npll_con[0], &npll_init_cfg);
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/* configure perihp aclk, hclk, pclk */
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aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
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--
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2.49.0
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